1. Field of the Invention
This invention relates broadly to field effect transistor storage circuits, and more particularly, relates to latch circuits.
2. Background Information
Latch circuits are well known in the art. A typical latch circuit includes a pair of cross-coupled field effect transistor (FET) devices which forms a bistable latch. Generally, the FET devices were N-type devices. In operating the latch, one node which is associated with a first side of the latch was pulled to a low-level potential by a data signal. This low-level potential switches an inverter which associated with a second side of the latch. The potential appearing on a node associated with the second side of the latch increases to a high-level and is fed back to an inverter associated with the first side of the latch clamping the first side to the low-level potential. Thus, the second side of the latch did not react to the data signal until the potential associated with the first side thereof was reduced to the low-level near ground potential. Therefore, a delay was inherent in the latch design wherein the second side had to wait for the first side to switch before the data signal would be stored. This latch design resulted in a slow speed of operation and the N-type devices occupied valuable space on an integrated circuit.